Dr. Baruch Zoltan Francisc
Professor




BARUCH, ZOLTAN FRANCISC

COMPUTER ARCHITECTURE

(in Romanian)

TODESCO, Cluj-Napoca, 2000, ISBN 973-99780-7-x (286 pages)









| Book Page | (Romanian only)


TABLE OF CONTENTS


1. INTRODUCTION

1.1. DIGITAL COMPUTERS
1.2. DIGITAL COMPUTER PROGRAMMING
1.3. DIGITAL COMPUTER MODEL
1.4. STRUCTURE OF THE PHYSICAL MACHINE

1.4.1. Central Processing Unit: Arithmetic and Logic Unit; Registers; Control Unit. 1.4.2. Memory Unit. 1.4.3. Input/Output Unit. 1.4.4. Interconnections

2. COMPUTER ARITHMETIC FUNDAMENTALS

2.1. NUMBER SYSTEMS
2.2. NUMBER SYSTEM CONVERSION

2.2.1. Integer Number Conversion. 2.2.2. Fractional Number Conversion. 2.2.3. Binary to Decimal Conversion

2.3. ARITHMETIC OPERATIONS WITH UNSIGNED NUMBERS

2.3.1. Addition. 2.3.2. Subtraction. 2.3.3. Multiplication. 2.3.4. Division

2.4. NUMBER REPRESENTATION
2.5. FIXED-POINT NUMBER REPRESENTATION

2.5.1. Signed-Number Representation. 2.5.2. Signed-Number Shifting Rules. 2.5.3. Operations with Fixed-Point Numbers: Addition of 2's Complement Numbers; Subtraction of 2's Complement Numbers

2.6. FLOATING-POINT NUMBER REPRESENTATION

2.6.1. Principles. 2.6.2. Number Representation in the IEEE 754 Format

2.7. CODES

2.7.1. Binary-Decimal Codes. 2.7.2. Error-Detecting Codes. 2.7.3. Error-Correcting Codes. 2.7.4. Alphanumeric Codes: ASCII; Unicode and ISO/IEC 10646

3. DIGITAL LOGIC CIRCUITS

3.1. BOOLEAN ALGEBRA ELEMENTS

3.1.1. Boolean Operators and Boolean Functions. 3.1.2. Postulates of Boolean Algebra. 3.1.3. Fundamental Theorems of Boolean Algebra

3.2. LOGIC GATES
3.3. CANONIC FORMS OF BOOLEAN FUNCTIONS
3.4. MINIMIZATION OF BOOLEAN FUNCTIONS

3.4.1. Algebraic Method. 3.4.2. Karnaugh-Map Method: Function Representation with Karnaugh Maps; Function Minimization with Karnaugh Maps; Minimization of Incompletely Specified Functions

3.5. COMBINATIONAL CIRCUITS

3.5.1. Code Converters. 3.5.2. Decoders: Address Decoder; BCD-to-Decimal Decoder; Using Decoders for Boolean Function Implementation. 3.5.3. Encoders. 3.5.4. Multiplexors. 3.5.5. Demultiplexors. 3.5.6. Programmable Logical Devices: ROMs; Programmable Logic Arrays; FPGA Circuits

3.6. SEQUENTIAL CIRCUITS

3.6.1. Overview of Sequential Circuits. 3.6.2. Flip-Flops: Asynchronous RS Flip-Flop; Synchronous RS Flip-Flop; Synchronous JK Flip-Flop; Synchronous D Flip-Flop; Synchronous T Flip-Flop; Master-Slave Flip-Flops; Integrated Flip-Flops. 3.6.3. Synthesis of Sequential Circuits. 3.6.4. Registers: Memory Registers; Shift Registers; Serial-to-Parallel Registers; Universal Registers. 3.6.5. Counters: Asynchronous Counters; Synchronous Counters

4. CENTRAL PROCESSING UNIT

4.1. CPU STRUCTURE
4.2. REGISTERS

4.2.1. User Registers. 4.2.2. Control and Status Registers

4.3. STACK MEMORY
4.4. INSTRUCTION EXECUTION

4.4.1. Fetch Cycle. 4.4.2. Execution Cycle. 4.4.3. Interrupt Cycle. 4.4.4. I/O Operations

4.5. THE INTEL PROCESSORS

4.5.1. Overview of the Intel Processors. 4.5.2. The Intel P6 Family Processors' Microarchitecture: General Presentation of the Microarchitecture; Detailed Presentation of the Microarchitecture

5. INSTRUCTION SETS

5.1. MACHINE INSTRUCTION ELEMENTS
5.2. ASSEMBLY LANGUAGES
5.3. NUMBER OF ADDRESSES PER INSTRUCTION
5.4. INSTRUCTION TYPES

5.4.1. Data Transfers. 5.4.2. Arithmetic Instructions. 5.4.3. Logical Instructions. 5.4.4. Branch and Call Instructions. 5.4.5. System Control Instructions. 5.4.6. I/O Instructions

5.5. ADDRESSING MODES

5.5.1. Immediate Addressing. 5.5.2. Direct Addressing. 5.5.3. Indirect Addressing. 5.5.4. Register Addressing. 5.5.5. Register Indirect Addressing. 5.5.6. Displacement Addressing: Relative Addressing; Base-Register Addressing; Indexed Addressing. 5.5.7. Stack Addressing

5.6. INSTRUCTION FORMAT

5.6.1. Instruction Length. 5.6.2. Bit Allocation. 5.6.3. Variable-Length Instructions

6. ARITHMETIC AND LOGIC UNIT

6.1. CIRCUITS FOR ADDING TWO BINARY DIGITS
6.2. OPERATIONS WITH FIXED-POINT NUMBERS

6.2.1. Binary Addition: Serial Adder; Parallel Adder. 6.2.2. Binary Multiplication: Direct Multiplication; Booth's Method; Higher-Radix Multiplication. 6.2.3. Binary Division: Principle of Binary Division; Binary Division Methods; Restoring Division Method; Non-Restoring Division Method

6.3. OPERATIONS WITH FLOATING-POINT NUMBERS

6.3.1. Floating-Point Addition and Subtraction. 6.3.2. Floating-Point Multiplication and Division. 6.3.3. Precision Considerations

7. CONTROL UNIT

7.1. MICRO-OPERATIONS

7.1.1. Fetch Cycle. 7.1.2. Indirect Cycle. 7.1.3. Execution Cycle. 7.1.4. Interrupt Cycle. 7.1.5. Instruction Cycle

7.2. CONTROL OF THE CPU

7.2.1. Functional Requirements of the Control Unit. 7.2.2. Control Signals. 7.2.3. Control Unit Example

7.3. INTERNAL CPU ORGANIZATION
7.4. IMPLEMENTATION OF THE CONTROL UNIT

7.4.1. Control Units with One-Hot Implementation. 7.4.2. Control Units with a Decoder. 7.4.3. Microprogrammed Control Units: Principle of Microprogrammed Control Units; Structure of Microprogrammed Control Units; Microinstruction Sequencing

8. MEMORY UNIT

8.1. CHARACTERISTICS OF MEMORY SYSTEMS
8.2. MEMORY HIERARCHY
8.3. SEMICONDUCTOR MEMORY

8.3.1. Semiconductor Memory Types. 8.3.2. Semiconductor Memory Organization

8.4. STACK MEMORY

8.4.1. Types of Stack Memories: Stack Implemented in Memory; Hardwired Stack; Partial-Hardwired Stack. 8.4.2. Stack-Oriented Computers: The Polish Notation for Arithmetic Expressions; Evaluation of Postfix Expressions

8.5. CACHE MEMORY

8.5.1. Principle of Cache Memory. 8.5.2. Characteristics of Cache Memory: Size; Mapping Function; Block Replacement Policy; Write Policy

9. I/O UNIT

9.1. I/O UNIT STRUCTURE
9.2. TYPES OF PERIPHERAL DEVICES
9.3. I/O MODULES

9.3.1. I/O Module Function. 9.3.2. I/O Module Structure

9.4. THE EXTERNAL INTERFACE
9.5. DATA TRANSFER METHODS

9.5.1. Programmed Transfer: Principle of Programmed Transfer; I/O Commands; I/O Instructions. 9.5.2. Interrupt-Driven Transfer. 9.5.3. Direct Memory Access. 9.5.4. Transfer by I/O Channels: Principle of Transfer by I/O Channels; CPU-I/O Channel Communication

BIBLIOGRAPHY