1.1 INTRODUCTION
1.2 XILINX FPGA DEVICES

1.2.1 Xilinx XC2000
1.2.2 Xilinx XC3000
1.2.3 Xilinx XC4000
1.2.4 Xilinx Software Tools

1.3 ALTERA FPGA DEVICES

1.3.1 General Structure of Altera FPGA Devices
1.3.2 The Altera Flex 8000 and Flex 10K FPGA Devices
1.3.3Altera Software Tools

1.4 ACTEL FPGA DEVICES

1.4.1 General Structure of Actel FPGA Devices
1.4.2 Actel Software Tools

1.5 AT&T FPGA DEVICES
1.6 QUICKLOGIC FPGA DEVICES
1.7 ARCHITECTURAL RESEARCH IN THE FIELD OF FPGA DEVICES

2.1 INTRODUCTION
2.2 XC4000 FAMILY

2.2.1 Description of the Internal Structure
2.2.2 Configurable Logic Blocks (CLBs): Function Generators; Internal Flip-Flops; Internal Latches (XC4000X Only); Clock Input; Clock Enable; Set/Reset; Data Inputs and Outputs; Control Signals; Using Flip-Flops and Latches; Using Function Generators as RAM; Fast Carry Propagation Logic
2.2.3 Input/Output Blocks: Input Signals from the IOB to the FPGA Circuit; Registered Inputs; IOB Output Signals; Controlling the Speed of Signal Transition (Slew Rate); The Global Line to Control the Three-State Outputs
2.2.4 Internal Three-State Buffers: Three-State Buffer Modes; Three-State Buffer Examples
2.2.5 Wide Internal Decoders
2.2.6 Internal Oscillator
2.2.7 Programmable Interconnects: CLB Routing Connections; IOB Routing Connections; Global Networks and Buffers
2.2.8 Boundary Scan: Data Registers; Instruction Set; Bit Sequence; Including Boundary Scan Features in Schematics
2.2.9 Configuration of FPGA Devices: Dedicated Pins to Select the Configuration Mode; Configuration Modes; Configuration Data Format; Configuration Sequence

2.3 XC5200 FAMILY

2.3.1 Description of the Internal Structure
2.3.2 VersaBlock Modules: Local Interconnects and Versatile Logic
2.3.3 Configurable Logic Blocks
2.3.4 Internal Oscillator
2.3.5 Global Reset Signal
2.3.6 Routing of VersaBlock Modules: Local Interconnection Matrix; Direct Interconnections
2.3.7 General Routing Matrix: Single- and Double-Length Lines; Longlines; Global Lines; VersaRing Input/Output Interface
2.3.8 Input/Output Blocks
2.3.9 Configuration of XC5200 FPGA Devices

2.4 SECOND-GENERATION XC6200 FPGA DEVICES

2.4.1 Logical and Physical Organization
2.4.2 Cells, Logic Blocks and Groups, Logic Units
2.4.3 Interconnection Resources: "Magical" Interconnections; Global Interconnections
2.4.4 Logic Cell
2.4.5 Input/Output Blocks (IOBs)
2.4.6 Configuration of XC6200 Series

3.1 COMPONENTS OF XILINX FOUNDATION SERIES DESIGN ENVIRONMENT

3.1.1 Design Entry Tools
3.1.2 Logic Synthesis Tools
3.1.3 Design Verification Tools
3.1.4 FPGA Device Configuration Tools
3.1.5 Framework Support Tools

3.2 SCHEMATIC EDITOR

3.2.1 Symbols and Libraries
3.2.2 Circuit Verification
3.2.3 Interfaces
3.2.4 Operations of the ACTIVE-CAD Schematic Editor

3.3 SIMULATOR

3.3.1 Creating the Circuit Model
3.3.2 Selecting the Test Points
3.3.3 Creating and Applying the Stimuli
3.3.4 Analysis of Simulation Results: Functional Simulation; Unit Delay Simulation Mode; Glitch Simulation Mode; Timing Simulation

3.4 HARDWARE DESCRIPTION LANGUAGE EDITOR

3.4.1 Advantages of Using Hardware Description Languages (HDLs) for Designing with FPGA Devices
3.4.2 Design Using Hardware Description Languages
3.4.3 Design Methodologies

3.5 FINITE-STATE MACHINE EDITOR
3.6 EPIC DESIGN EDITOR

3.6.1 EPIC Interface: Main EPIC Window; EPIC List Dialog Window; Layer Visibility Dialog Window; Command Line Dialog Window

3.7 FLOORPLANNER

3.7.1 Preliminary Requirements
3.7.2 Floorplanner Features
3.7.3 File Types: Input Files; Output Files
3.7.4 Design Methodologies: Place and Route before Floorplanning; Floorplanning Prior to Place and Route; Iterative Floorplanning; Incremental Design Changes

3.8 CONSTRAINT EDITOR

3.8.1 Constraint Editor Windows
3.8.2 Specifying Constraints: Constraints Defined in the Global Secondary Window; Constraints Defined in the Ports Secondary Window; Constraints Defined in the Advanced Secondary Window
3.8.3 Input and Output Files

3.9 LOGIBLOX

3.9.1 Designing with User-Defined Logic Modules
3.9.2 Advantages of Designing with LogiBLOX
3.9.3 LogiBLOX Inputs and Outputs
3.9.4 Integrating LogiBLOX in the Schematic Design Flow
3.9.5 Integrating LogiBLOX in the HDL Design Flow

3.10 HARDWARE DEBUGGER

3.10.1 Hardware Debugger Features
3.10.2 Relationship between Design and Architecture
3.10.3 Design Entry and Generation of the Configuration File: Configuration Mode; Selecting the Board; Configuration of One or Several Devices; Connecting the Cables
3.10.4 Creating a Design to Use the Hardware Debugger: Preparing a Design for Downloading; Preparing a Design for Verification and Debugging
3.10.5 Downloading Cable
3.10.6 Debugging

3.11. TIMING ANALYSER

3.11.1 Inputs and Outputs
3.11.2 Features: Interface Features; Features Related to Reports; Filtering Commands; Features Related to Macros; Features Related to Aborting the Analysis
3.11.3 Principles of Timing Analysis: Main Path Types
3.11.4 Problems of Timing Analysis: Feedback Loops; Timing Constraints; Clock Skew; Off-Chip Delay
3.11.5 Basic Procedure for Timing Analysis

3.12 JTAG PROGRAMMER

3.12.1 Programming and Verification
3.12.2 Non-Volatile Security of Devices
3.12.3 Required Files: JEDEC Files; BSDL Files; BIT Files
3.12.4 Creating New Serial Descriptions
3.12.5 In-System Configuration of CPLDs: Concurrent Mode; HIGHZ Mode Instead of BYPASS Mode
3.12.6 Selecting the Components for Programming (FPGA)
3.12.7 Connecting Devices in a Boundary-Scan Chain: Design Rules for Boundary-Scan and ISP Systems
3.12.8 FPGA Devices: Configuration Files; Device Initialization; Verifying the Device Configuration
3.12.9 Boundary-Scan: JTAG TAP Controller; JTAG Instructions Supported by FastFLASH Components

3.13 PROM FILE FORMATTER

3.13.1 Xilinx PROM Files
3.13.2 Display Area for PROM File Descriptions
3.13.3 Types of Files Used: Input Files; Output Files
3.13.4 Bit Interchanging in PROM Files
3.13.5 Implementing Applications
3.13.6 Preparing Multiple Configurations: Reconfiguring a Chain from a Serial PROM; Reconfiguring a Device or a Device Chain from a Parallel PROM; Configuring Multiple Chains from a Parallel PROM

3.14 DESIGN MANAGER

3.14.1 Introduction
3.14.2 Design Flow
3.14.3 Basic Operations of Design Manager
3.14.4 Basic Procedure for Managing Projects
3.14.5 Basic Operations of Flow Engine
3.14.6 Running Multi-Pass Place and Route
3.14.7 Running Re-Entrant Routing
3.14.8 Specifying Implementation, Simulation, and Configuration Options
3.14.9 Guiding a Design

3.15 PROJECT MANAGER

3.15.1 Hierarchy Browser
3.15.2 Project Flowchart Area
3.15.3 Message Display Area

3.16 LIBRARY MANAGER

4.1 STRATEGIES FOR DESIGNING WITH FPGA DEVICES
4.2 DESIGN ENTRY WITH A SCHEMATIC EDITOR
4.3 SPECIFYING THE DESIGN IN A HARDWARE DESCRIPTION LANGUAGE
4.4 EFFICIENT IMPLEMENTATION OF LINEAR FEEDBACK COUNTERS

4.4.1 LFSR Counters

4.5 EFFICIENT IMPLEMENTATION OF SHIFT REGISTERS
4.6 EFFICIENT IMPLEMENTATION OF PSEUDO-RANDOM SEQUENCE GENERATORS
4.7 EFFICIENT IMPLEMENTATION OF QUEUE MEMORIES (FIFO)

4.7.1 Control Logic
4.7.2 State Logic
4.7.3 FIFO Memory Array
4.7.4 FIFO Memory Timing Diagram
4.7.5 Physical Implementation
4.7.6 Non-Recommended Approach
4.7.7 Solution with Synchronous RAM
4.7.8 Simplified FIFO Memory with Synchronous RAM
4.7.9 FIFO Memory Implemented with Dual-Ported Synchronous RAM

4.8 EFFICIENT IMPLEMENTATION OF STATE MACHINES

4.8.1 Synchronous Counters
4.8.2 Waveform Generator
4.8.3 Simple State Machines
4.8.4 One-Hot Encoded State Machines
4.8.5 Complex State Machines

4.9 CONFIGURATION OF FPGA DEVICES BY CONNECTING TO A MICROPROCESSOR SYSTEM

4.9.1 The Interface with the Microprocessor
4.9.2 Ultra-Fast Reconfiguration Scheme

5.1 INTRODUCTION
5.2 CHOOSING THE SOLUTION

5.2.1 Implementing the Serial Distributed Arithmetic
5.2.2 Implementing the Shift Register Chain

5.3 SINGLE-CHIP DEVICE TO PERFORM CONVOLUTION IN REAL-TIME
5.4 GENERALIZED m x m CONVOLUTION DEVICE
5.5 CONCLUSIONS AND POSSIBLE DEVELOPMENTS