Dr. Baruch Zoltan Francisc
Professor




BARUCH, ZOLTAN FRANCISC

STRUCTURE OF COMPUTER SYSTEMS

(in Romanian)

Editura Albastră, Cluj-Napoca, 2005, ISBN 973-650-143-4 (448 pages)










TABLE OF CONTENTS


1. INTRODUCTION

1.1. TAXONOMIES OF COMPUTER ARCHITECTURES
1.2. OVERVIEW OF COMPUTER ARCHITECTURES

1.2.1. Multiprocessors. 1.2.2. Multicomputers. 1.2.3. Multi-Multiprocessors. 1.2.4. Data Flow Architectures. 1.2.5. Array Processors. 1.2.6. Pipelined Vector Processors. 1.2.7. Systolic Arrays. 1.2.8. Hybrid Architectures. 1.2.9. Artificial Neural Networks. 1.2.10. Fuzzy Logic Processors

1.3. PERFORMANCE METRICS

1.3.1. Execution Time. 1.3.2. CPU Time. 1.3.3. MIPS. 1.3.4. MFLOPS. 1.3.5. Other Performance Measurements. 1.3.6. Benchmark Programs: Comparing and Summarizing Performance; The Evolution of Benchmark Programs; CPU95; CPU2000. 1.3.7. Quality Factors

1.4. QUANTITATIVE PRINCIPLES OF COMPUTER DESIGN

1.4.1. Amdahl's Law. 1.4.2. Principle of Locality

1.5. PROBLEMS

2. DESIGN REPRESENTATION AND METHODOLOGY

2.1. SYSTEM REPRESENTATION
2.2. LEVELS OF DESCRIPTION
2.3. DESIGN PROCESS

2.3.1. System-Level Synthesis. 2.3.2. High-Level Synthesis. 2.3.3. Register-Transfer Level Synthesis. 2.3.4. Logic-Level Synthesis. 2.3.5. Technology Mapping

2.4. VHDL HARDWARE DESCRIPTION LANGUAGE

2.4.1. Hardware Description Languages. 2.4.2. Introduction to VHDL. 2.4.3. VHDL Styles of Description. 2.4.4. The Time Model in VHDL. 2.4.5. Simulation of a Model

3. ARITHMETIC-LOGIC UNIT

3.1. ADDITION

3.1.1. Full Adder. 3.1.2. Ripple Carry Adder. 3.1.3. Carry Lookahead Adder. 3.1.4. Carry Select Adder. 3.1.5. Carry Save Adder. 3.1.6. Serial Adder. 3.1.7. Decimal Adder

3.2. MULTIPLICATION

3.2.1. Shift-and-Add Multiplication. 3.2.2. Booth's Technique. 3.2.3. Higher-Radix Multiplication. 3.2.4. Array Multipliers. 3.2.5. Wallace Tree. 3.2.6. Shifting Over Zeros and Ones

3.3. DIVISION

3.3.1. Restoring Division. 3.3.2. Nonrestoring Division. 3.3.3. SRT Division. 3.3.4. Other Fast Division Methods. 3.3.5. Array Divider. 3.3.6. Signed Division

3.4. FLOATING-POINT NUMBERS AND OPERATIONS

3.4.1. Floating-Point Representation: Principles; IEEE 754 Floating-Point Standard. 3.4.2. Floating-Point Operations: Floating-Point Addition and Subtraction; Floating-Point Multiplication and Division; Precision Considerations

3.5. PROBLEMS

4. MEMORY SYSTEMS

4.1. MEMORY HIERARCHY
4.2. MEMORY TYPES
4.3. MEMORY PERFORMANCE MEASURES
4.4. SEMICONDUCTOR MAIN MEMORY

4.4.1. Memory Cell and Memory Unit. 4.4.2. Memory Organization. 4.4.3. Memory Design. 4.4.4. Example of a Commercial Memory Circuit. 4.4.5. Performance Parameters of DRAM memories. 4.4.6. Technologies for DRAM Memories: Categories of DRAM Memories; FPM DRAM; EDO DRAM; BEDO DRAM; SDRAM; HSDRAM; ESDRAM; Virtual Channel Memory; FCRAM; DDR SDRAM; DDR II SDRAM; Rambus DRAM; IRAM; Memory Modules

4.5. INTERLEAVED MEMORY
4.6. ASSOCIATIVE MEMORY
4.7. CACHE MEMORY

4.7.1. Principles. 4.7.2. Cache Memory Organization. 4.7.3. Cache Memory Operation. 4.7.4. Address Mapping: Associative Mapping; Direct Mapping; Set-Associative Mapping. 4.7.5. Replacement Policies. 4.7.6. Cache Memory Types. 4.7.7. Cache Memory Performance. 4.7.8. Cache Memory Coherence

4.8. VIRTUAL MEMORY

4.8.1. Principles. 4.8.2. Address Translation. 4.8.3. Paging. 4.8.4. Segmentation. 4.8.5. Paging and Segmentation. 4.8.6. Memory Allocation: Non-Preemptive Allocation; Preemptive Allocation; Replacement Policies. 4.8.7. Memory Management in the Intel Architecture: Memory Management Overview; Segmentation; Paging

4.9. PROBLEMS

5. PIPELINING

5.1. PIPELINE STRUCTURE
5.2. PIPELINE PERFORMANCE MEASURES
5.3. PIPELINE TYPES
5.4. INSTRUCTION PIPELINES

5.4.1. Principle of Instruction Pipelines. 5.4.2. The Fetching Problem. 5.4.3. The Bottleneck Problem. 5.4.4. The Structural Hazard Problem. 5.4.5. The Data Hazard Problem: Data Dependencies; Tomasulo's Method; Scoreboard Method. 5.4.6. The Control Hazard Problem: Branch Instructions; Branch Prediction; Delayed Branching; Multiple Prefetching. 5.4.7. The Intel Architecture Processors' Pipeline: Fetch/Decode Unit; Instruction Pool; Dispatch/Execute Unit; Retirement Unit; Bus Interface Unit. 5.4.8. Throughput Improvements of an Instruction Pipeline: Superscalar Processing; Superpipeline Processing; Very Long Instruction Word; Explicitly Parallel Instruction Computing; Comparison of Throughput Improvement Methods

5.5. ARITHMETIC PIPELINES

5.5.1. Principle of Arithmetic Pipelines. 5.5.2. Design of an Arithmetic Pipeline. 5.5.3. Arithmetic Pipelines with Feedback. 5.5.4. Pipelined Multipliers. 5.5.5. Systolic Arrays

5.6. PIPELINE CONTROL

5.6.1. Scheduling. 5.6.2. Scheduling Static Pipelines. 5.6.3. Scheduling Dynamic Pipelines

5.7. PROBLEMS

6. RISC ARCHITECTURES

6.1. INTRODUCTION
6.2. CAUSES FOR INCREASED ARCHITECTURAL COMPLEXITY
6.3. ADVANTAGES OF RISC ARCHITECTURES
6.4. THE USE OF A LARGE NUMBER OF REGISTERS
6.5. CHARACTERISTICS OF RISC ARCHITECTURES
6.6. COMPARISON BETWEEN RISC AND CISC ARCHITECTURES
6.7. APPLICATIONS OF RISC PROCESSORS
6.8. MIPS ARCHITECTURE

6.8.1. Introduction. 6.8.2. MIPS R2000. 6.8.3. MIPS R3000. 6.8.4. MIPS R3500. 6.8.5. MIPS R3001. 6.8.6. MIPS R4000. 6.8.7. MIPS R4300i. 6.8.8. MIPS R4400. 6.8.9. MIPS R4600, R4650 and R4700. 6.8.10. MIPS R6000. 6.8.11. MIPS-III Architecture: Hardware Details; Software Details; Floating-Point Unit; Cache Memories; Memory Management; Exceptions. 6.8.12. MIPS R8000 and R10000: Introduction; Hardware Details; Software Details; Floating-Point Unit; Cache Memories; Memory Management. 6.8.13. MIPS R5000: Overview; Increased 3D Graphics Performance; Multi-Processing Support; Secondary Cache Memory Support; Flexible Clocking Mechanism. 6.8.14. Summary

6.9. SPARC ARCHITECTURE

6.9.1. Introduction. 6.9.2. HyperSPARC. 6.9.3. SuperSPARC. 6.9.4. MicroSPARC and MicroSPARC-II. 6.9.5. SPARClite. 6.9.6. UltraSPARC-I. 6.9.7. UltraSPARC-II. 6.9.8. UltraSPARC-IIi: Overview; Block Diagram; Prefetch and Dispatch Unit; Integer Execution Unit; Floating-Point Unit; I/O Memory Management Unit; Memory Controller Unit; Load-Store Unit; Data and Instruction Cache Memories; External Cache Unit; Graphics Unit; The Visual Instruction Set. 6.9.9. UltraSPARC-III. 6.9.10. MAJC. 6.9.11. Summary

6.10. POWERPC ARCHITECTURE

6.10.1. Introduction. 6.10.2. PowerPC 601: Overview; Block Diagram; Instruction Unit; Execution Units; Cache Memory; Memory Management; Software Details; Exceptions. 6.10.3. PowerPC 602. 6.10.4. PowerPC 603 and 603e. 6.10.5. PowerPC 604 and 604e. 6.10.6. PowerPC 740 and 750: Overview; Block Diagram; Instruction Unit; Completion Unit; Integer Units; Floating-Point Unit; Load/Store Unit; System Register Unit; Memory Management Units; On-Chip Cache Memories; L2 Cache Memory; Bus Interface Unit. 6.10.7. PowerPC 7400: Overview; AltiVec Vector Permute Unit; AltiVec Vector Arithmetic-Logic Unit. 6.10.8. PowerPC 850 and 860: Overview; Block Diagram; The PowerPC Core; System Interface Unit; PCMCIA Controller; Communications Processor Module; Differences between the MPC850 and MPC860 Processors. 6.10.9. Summary

6.11. PROBLEMS

BIBLIOGRAPHY