Dr. Baruch Zoltan Francisc
Professor




BARUCH, ZOLTAN FRANCISC

STRUCTURE OF COMPUTER SYSTEMS
WITH APPLICATIONS

(in Romanian)

TODESCO, Cluj-Napoca, 2001, ISBN 973-8198-13-5 (350 pages)








TABLE OF CONTENTS



1. DIDACTIC COMPUTER

1.1. OVERVIEW OF THE DIDACTIC COMPUTER
1.2. INSTRUCTIONS OF THE DIDACTIC COMPUTER

1.2.1. Word Structure. 1.2.2. Instruction Set. 1.2.3. Example Programs

1.3. STRUCTURE OF THE DIDACTIC COMPUTER

1.3.1. General Structure. 1.3.2. Control Signals. 1.3.3. Detailed Structure

1.4. APPLICATIONS

2. BINARY MULTIPLICATION AND DIVISION CIRCUITS

2.1. BINARY MULTIPLICATION

2.1.1. Binary Multiplication Methods. 2.1.2. Direct Multiplication. 2.1.3. Booth Multiplication. 2.1.4. Multiplication on Groups of Bits

2.2. BINARY DIVISION

2.2.1. Principle of Binary Division. 2.2.2. Binary Division Methods. 2.2.3. Restoring Division. 2.2.4. Nonrestoring Division

2.3. APPLICATIONS

3. DECIMAL MULTIPLICATION AND DIVISION CIRCUITS

3.1. DECIMAL MULTIPLICATION

3.1.1. Repeated-Addition Method. 3.1.2. Nine-Multiples-of-Multiplicand Method. 3.1.3. Right-and-Left-Hand Components Method

3.2. DECIMAL DIVISION

3.2.1. Restoring Division. 3.2.2. Nonrestoring Division. 3.2.3. Nine-Multiples-of-Divisor Method

3.3. APPLICATIONS

4. MICROPROGRAMMED COMPUTERS

4.1. PRINCIPLE OF MICROPROGRAMMED COMPUTERS

4.1.1. Introduction. 4.1.2. Horizontal and Vertical Microprogramming. 4.1.3. Structure of a Microprogrammed Control Unit

4.2. EXAMPLE OF COMPUTER WITH HORIZONTAL MICROPROGRAMMING

4.2.1. Datapath Structure. 4.2.2. Microinstruction Format. 4.2.3. Microinstruction Sequencing. 4.2.4. The Microassembly Language

4.3. EXAMPLE OF COMPUTER WITH VERTICAL MICROPROGRAMMING

4.3.1. Vertical Microinstructions. 4.3.2. Structure of Control Section

4.4. APPLICATIONS

5. THE ACTIVE-HDL DESIGN SYSTEM

5.1. OVERVIEW OF THE ACTIVE-HDL DESIGN SYSTEM
5.2. COMPONENTS OF THE ACTIVE-HDL DESIGN SYSTEM

5.2.1. Source Code Editor. 5.2.2. Block Diagram Editor. 5.2.3. State Machine Editor. 5.2.4. Compiler. 5.2.5. Simulator: Simulation Phases; Defining Stimulus; Running Simulation. 5.2.6. Waveform Editor. 5.2.7. Design Explorer. 5.2.8. Design Browser. 5.2.9. Library Manager: Library Structure; Library Manager Window; Operations with Libraries. 5.2.10. Console Window. 5.2.11. Processes Window. 5.2.12. Watch Window. 5.2.13. Call Stack Window. 5.2.14. Dataflow Window. 5.2.15. List Window

5.3. EXAMPLE DESIGN

5.3.1. Design Description. 5.3.2. Creating a New Design: Entering the Design Name; Creating a Source File; Adding Ports. 5.3.3. Editing and Compiling the Source Code: Describing the Architecture of the Counter; Specifying the Library for Compilation; Compilation. 5.3.4. Viewing the Design Structure. 5.3.5. Simulation: Initializing the Simulation; Assigning Stimulators; Running the Simulation; Editing the Waveforms; Tracking the Source Code; Setting Breakpoints; Enabling Breakpoints; Viewing the Simulation Results in Textual Form. 5.3.6. Adding a New File to the Design. 5.3.7. Using the State Machine Editor: Editing the State Machine Ports; Placing State Symbols; Editing a State Symbol; Adding Transitions; Editing Transitions; Adding Transition Conditions; Adding Actions for Output Generation; Specifying the State Machine Properties; Generating the Source Code. 5.3.8. Creating a Top Level File. 5.3.9. Compiling the Entire Design. 5.3.10. Simulating the Design

5.4. APPLICATIONS

6. BASIC ELEMENTS OF THE VHDL LANGUAGE

6.1. DESIGN UNITS
6.2. ENTITIES

6.2.1. Entity Names: Identifiers. 6.2.2. Entity Declarations. 6.2.3. Signals and Ports: The Concept of a Signal; Port Declarations; Port Modes; Port Types. 6.2.4. Generics

6.3. ARCHITECTURES

6.3.1. Architecture Declaration. 6.3.2. Signal Declaration. 6.3.3. Signal Assignments. 6.3.4. Styles of Architectural Descriptions: Functional Descriptions; Dataflow Descriptions; Structural Descriptions; Comparing Architectural Descriptions

6.4. MODELING FOR SIMULATION

6.4.1. Event-Driven Simulation. 6.4.2. Signal Drivers. 6.4.3. Simulation Cycle. 6.4.4. Multiple Drivers and Resolution Functions

6.5. MODELING FOR SYNTHESIS
6.6. APPLICATIONS

7. TYPES, ATTRIBUTES, AND OPERATORS IN THE VHDL LANGUAGE

7.1. DATA OBJECTS

7.1.1. Constants. 7.1.2. Variables. 7.1.3. Files

7.2. DATA TYPES

7.2.1. Data Type Overview: Data Type Classification; Synthesizable Data Types; Standard Types; Standard Operators. 7.2.2. Scalar Types: Enumeration Types; Integer Types; Floating Types; Physical Types. 7.2.3. Composite Types: Arrays; Records

7.3. ATTRIBUTES

7.3.1. Type Attributes. 7.3.2. Array Attributes. 7.3.3. Signal Attributes

7.4. OPERATORS

7.4.1. The Standard Operator Set and Their Precedence. 7.4.2. Logical Operators. 7.4.3. Relational Operators. 7.4.4. Shift Operators. 7.4.5. Arithmetic Operators. 7.4.6. Concatenation Operator

7.5. APPLICATIONS

8. SEQUENTIAL AND CONCURRENT STATEMENTS IN THE VHDL LANGUAGE

8.1. SEQUENTIAL STATEMENTS

8.1.1. Processes: Structure and Execution of a Process; Processes with Incomplete Sensitivity Lists; Wait Statement; Combinational and Sequential Processes. 8.1.2. Sequential Signal Assignment Statement: Sequential Assignment Statement Execution; Feedback; Inertial Delay; Transport Delay. 8.1.3. Variables: Declaring and Initializing Variables; Variable Assignment Statement. 8.1.4. If Statement: Syntax and Execution of an if Statement; Synthesis Interpretation of an if Statement; Incomplete if Statements; If Statements with Variables. 8.1.5. Case Statement. 8.1.6. Loop Statements: Loop Statement; While loop Statement; For loop Statement; Next Statement; Exit Statement. 8.1.7. Sequential assert Statement

8.2. CONCURRENT STATEMENTS

8.2.1. Structure and Execution of an Architecture. 8.2.2. Processes. 8.2.3. Concurrent Signal Assignment Statements: Simple Signal Assignment; Conditional Signal Assignment; Selected Signal Assignment; Block Statement; Concurrent assert Statement

8.3. EXAMPLES OF COMBINATIONAL CIRCUITS

8.3.1. Multiplexers. 8.3.2. Priority Encoders

8.4. EXAMPLES OF SEQUENTIAL CIRCUITS

8.4.1. Synchronous and Asynchronous Sequential Circuits. 8.4.2. Flip-Flops. 8.4.3. Registers. 8.4.4. Counters. 8.4.5. Resetting Synchronous Logic. 8.4.6. Three-State Buffers and Bidirectional Signals

8.5. APPLICATIONS

9. STATE MACHINES IN THE VHDL LANGUAGE

9.1. DESIGN EXAMPLE

9.1.1. Traditional Design. 9.1.2. Design Using the VHDL Language

9.2. DESIGN OF A MEMORY CONTROLLER
9.3. TECHNIQUES TO GENERATE THE OUTPUT SIGNALS

9.3.1. Outputs Decoded from State Bits. 9.3.2. Outputs Decoded in Parallel Output Registers. 9.3.3. Outputs Encoded within State Bits. 9.3.4. One-Hot Encoding

9.4. MEALY STATE MACHINES
9.5. OTHER DESIGN CONSIDERATIONS

9.5.1. State Encoding Using Enumeration Types. 9.5.2. Explicit State Encoding. 9.5.3. Fault Tolerance for One-Hot Machines

9.6. APPLICATIONS

10. STRUCTURAL DESIGN IN THE VHDL LANGUAGE

10.1. ADVANTAGES OF STRUCTURAL DESIGN
10.2. ELEMENTS OF A STRUCTURAL DESCRIPTION

10.2.1. Example of Structural Description. 10.2.2. Component Declaration. 10.2.3. Component Instantiation. 10.2.4. Direct Entity Instantiation. 10.2.5. Configuration Specification

10.3. LIBRARIES
10.4. PACKAGES

10.4.1. Package Declaration. 10.4.2. Package Body. 10.4.3. Packages with Component Declarations

10.5. GENERICS AND PARAMETERIZED COMPONENTS

10.5.1. Principle of Generics. 10.5.2. Defining Generic Entities. 10.5.3. Using Generic Components. 10.5.4. Types of Generic Parameters. 10.5.5. Building a Library of Components

10.6. GENERATE STATEMENT

10.6.1. For generate Statement. 10.6.2. If generate Statement. 8.6.3. Component Instances in Generate Statements

10.7. APPLICATIONS

11. SUBPROGRAMS IN THE VHDL LANGUAGE

11.1. THE ROLE OF SUBPROGRAMS
11.2. FUNCTIONS

11.2.1. Function Definition. 11.2.2. Using Functions. 11.2.3. Initial Values. 11.2.4. Functions with Unconstrained Parameters. 11.2.5. Unconstrained Return Values. 11.2.6. Multiple Return Statements. 11.2.7. Function Overloading. 11.2.8. Type Conversion Functions: Built-In Type Conversions; User-Defined Type Conversions. 11.2.9. Functions as Alternative to Component Instantiation.11.2.10. Problematic Functions for Synthesis. 11.2.11. Defining Operators as Functions: Built-In Operators; Operator Overloading. 11.2.12. Standard Functions. 11.2.13. Placement of Function Definitions

11.3. PROCEDURES

11.3.1. Procedure Definition. 11.3.2. Procedure Call. 11.3.3. Procedures with Unconstrained Parameters. 11.3.4. Parameters of Mode Inout. 11.3.5. Signals Used as Parameters. 11.3.6. Procedure Overloading

11.4. APPLICATIONS

12. THE DLX COMPUTER

12.1. ARCHITECTURE OF THE DLX COMPUTER

12.1.1. Register Set. 12.1.2. Structure of the Pipelined Datapath and Instruction Execution. 12.1.3. Hazards

12.2. THE DLX ASSEMBLY LANGUAGE

12.2.1. Expressions. 12.2.2. Directives. 12.2.3. Instruction Set: Data Transfer Instructions; Arithmetic and Logical Instructions; Control Instructions; Floating-Point Instructions

12.3. THE WinDLX SIMULATOR

12.3.1. Overview. 12.3.2. System Function Calls: Open a File; Close a File; Read a Block from a File; Write a Block to a File; Formatted Output to the Standard Output Device

12.4. USING THE WinDLX SIMULATOR

12.4.1. Starting and Configuring the Simulator. 12.4.2. Loading the Test Programs. 12.4.3. Simulating: Pipeline Window; Code Window; Clock Cycle Diagram Window; Breakpoint Window; Register Window; Statistics Window

12.5. APPLICATIONS


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