PERFORMANCE METRICS

• Execution Time
• CPU Time
• MIPS
• MFLOPS
• Other Performance Measurements
• Benchmark Programs: Comparing and Summarizing Performance; The Evolution of Benchmark Programs; SPEC CPU2006

QUANTITATIVE PRINCIPLES OF COMPUTER DESIGN

• Amdahl's Law
• Locality of Reference

ADDITION

• Full Adder
• Ripple Carry Adder
• Carry Lookahead Adder
• Carry Select Adder
• Carry Save Adder
• Serial Adder
• Binary-Coded Decimal Adder

MULTIPLICATION

• Shift-and-Add Multiplication
• Booth's Technique
• Wallace Tree
• Shifting Over Zeros and Ones
• Array Multiplier

DIVISION

• Restoring Division
• Nonrestoring Division
• SRT Division
• Other Fast Division Methods
• Array Divider
• Signed Division

FLOATING-POINT NUMBERS AND OPERATIONS

• Floating-Point Representation: Principles; IEEE 754 Floating-Point Standard
• Floating-Point Operations: Floating-Point Addition and Subtraction; Floating-Point Multiplication and Division
• Precision Considerations

MEMORY HIERARCHY
MEMORY TYPES
MEMORY PERFORMANCE MEASURES
SEMICONDUCTOR MAIN MEMORY

• Memory Cell and Memory Unit
• Memory Organization
• Memory Design
• Example of a Commercial Memory Circuit
• Performance Parameters of DRAM memories
• Technologies for DRAM Memories: Categories of DRAM Memories; FPM DRAM; EDO DRAM; BEDO DRAM; SDRAM; HSDRAM; ESDRAM; Virtual Channel Memory; FCRAM; DDR SDRAM; DDR II SDRAM; RDRAM and DRDRAM; IRAM; Memory Modules

INTERLEAVED MEMORY
ASSOCIATIVE MEMORY
CACHE MEMORY

• Principle of Cache Memory
• Cache Memory Organization
• Cache Memory Operation
• Address Mapping: Associative Mapping; Direct Mapping; Set-Associative Mapping
• Replacement Policies: Random Replacement; Least Frequently Used; Least Recently Used
• Cache Memory Types
• Cache Memory Performance
• Cache Memory Coherence

VIRTUAL MEMORY

• Principle of Virtual Memory
• Address Translation
• Paging
• Segmentation
• Paging and Segmentation
• Memory Allocation: Non-Preemptive Allocation; Preemptive Allocation; Replacement Policies
• Memory Management in the Intel Architecture: Memory Management Overview; Segmentation; Paging

PIPELINE STRUCTURE
PIPELINE PERFORMANCE MEASURES
PIPELINE TYPES
INSTRUCTION PIPELINES

• Principle of Instruction Pipelines
• The Fetching Problem
• The Bottleneck Problem
• The Structural Hazard Problem
• The Data Hazard Problem: Data Dependencies; Tomasulo's Method; Scoreboard Method
• The Control Hazard Problem: Branch Instructions; Branch Prediction; Delayed Branching; Multiple Prefetching
• The Intel Architecture Processors' Pipeline: Fetch/Decode Unit; Instruction Pool; Dispatch/Execute Unit; Retirement Unit; Bus Interface Unit
• Throughput Improvements of an Instruction Pipeline: Superscalar Processing; Superpipeline Processing; Very Long Instruction Word; Explicitly Parallel Instruction Computing; Comparison of Throughput Improvement Methods

ARITHMETIC PIPELINES

• Principle of Arithmetic Pipelines
• Design of an Arithmetic Pipeline
• Arithmetic Pipelines with Feedback
• Pipelined Multipliers
• Systolic Arrays

PIPELINE CONTROL

• Scheduling
• Scheduling Static Pipelines
• Scheduling Dynamic Pipelines

INTRODUCTION
CAUSES FOR INCREASED ARCHITECTURAL COMPLEXITY
ADVANTAGES OF RISC ARCHITECTURES
THE USE OF A LARGE NUMBER OF REGISTERS
CHARACTERISTICS OF RISC ARCHITECTURES
COMPARISON BETWEEN RISC AND CISC ARCHITECTURES
APPLICATIONS OF RISC PROCESSORS
POWERPC ARCHITECTURE

• Introduction
• PowerPC 601
• PowerPC 603 and 603e
• PowerPC 7400

TAXONOMY OF COMPUTER ARCHITECTURES
PARALLEL ARCHITECTURES

• Multiprocessors
• Multicomputers
• Multi-multiprocessors
• Data Flow Architectures
• Array Processors
• Pipelined Vector Processors
• Systolic Arrays
• Hybrid Architectures

CURRENT DIRECTIONS

• Artificial Neural Networks
• Fuzzy Logic Processors
• Optical Computing
• Grid Computing
• Quantum Computing