|  Silicon
Solutions  |  Design
Resources  |  System
Resources  |  Services  |  Documentation  |

Home : Products
& Services : System
Solutions :

Xilinx BSDL Files

Entire
Site Data
Sheets User
Guides Software Manuals
Application
Notes Package
Drawings White
Papers Cust.
Notifications Answer
Database Answer
Archive Tech
Tips Online
Store IP
Solutions Products /
Services XCELL
Journals Press
Releases

Advanced

Boundary Scan Testing - Augmenting Traditional
Methods:
Electronic systems continue to increase in complexity and
functionality with board space always at a premium. Smaller more dense
packages including ultra dense ball-grid arrays (BGAs) and chip scale
packages have resulted in reduced access to device pins with a possible
reduction in test coverage. To gain access to these pins, users are
utilizing a combination of test methods to guarantee greater board test
coverage. One of these methods is boundary scan testing. Traditional
"bed-of-nails" testing uses Automatic Test Equipment (ATEs) which are
being augmented and expanded with boundary scan techniques. When using
high density packages and complex multi-function/ voltage I/Os like those
found on Virtex and Spartan devices, users must be sure that the Boundary
Scan Description Language Files (BSDL) used to describe the operation of
all pins are of the highest quality.

BSDL files are generated for
every part and package combination of IEEE 1149.1 compatable devices
produced by Xilinx. These files can be used by third party boundary scan
tools available from a variety of vendors to generate test vectors and
perform the tests. BSDL files are also used by Xilinx programming software
when configuring devices through Boundary Scan. It is obvious from the
many different uses of these files how important the quality is.

Key to Flawless Boundary Scan Operation:
Agilent IEEE Std
1149.1 compiler
GenRad BSDL Syntax Checker
Asset Intertech
Compiler
Intellitech Syntax
Checker

Additionally to guarantee that the BSDL files exactly
describe the operation of each pin, Xilinx uses an independent third party
boundary scan tool vendor -Intellitech - to verify the actual silicon
against the BSDL.

Advanced & Preliminary BSDL Files:
BSDL files for devices
that have not undergone complete syntax and functionality testing are
marked as advanced or preliminary. These files can be created quickly and
are of a high quality.

Final BSDL Files:
Files marked
Final have undergone all the tests for syntax and hardware verification.

Independent Third Party Testing of Xilinx BSDL files

Intellitech's Check for Compliance:
Xilinx BSDL's are checked
for 1149.1 compliance with the Intellitech Eclipse product using 'strict'
BSDL syntax checking. Every semantic check described in the IEEE
1149.1b-1994 (the standard for BSDL syntax) is performed using strict
parsing. Test patterns are then generated from the BSDL file that include
unique tests for every I/O pin. Each Xilinx device/package combination is
tested on the Intellitech RCT (Reduced Contact Tester). The test patterns
include verification of Test-Logic-Reset and TAP controller
operation,
BYPASS/IDCODE/USERCODE instructions and registers, and pin mapping of the
boundary register to every input/output/bidir/clock pin and control cell.
Finally, each device is tested for 1149.1 compliance after the device is
programmed by downloading a design and using the RCT tester to verify post
configuration compliance..

Check Input/ Outputs:
Test patterns are then generated from
the BSDL that include unique tests for every I/O pin. The test patterns
include verification of Test-Logic-Reset and TAP controller operation,
BYPASS/IDCODE/USERCODE instructions and registers, and pin mapping of the
boundary register to every input/output/bidir/clock pin and control cell.

Hardware Verification:
Each Xilinx device/package combination
is tested on the Intellitech RCT (Reduced Contact Tester). A custom
adapter and socket is used to interface even the most complex microBGA
packages to the tester. This allows the tester's parallel I/O pins (up to
640) to connect to the IC pins for full
1149.1 pin verification.

Post Configuration Test:
In addition, each device family is
tested for 1149.1 compliance after
the device is programmed. A small
design is downloaded and the same operations on the RCT are verified. This
verifies that nothing in the design of the device will affect the
operation of the 1149.1 logic.

ISP
Standard & Specifications

Trademarks
Legal Information
Privacy
Policy

| Silicon
Solutions | Design
Resources | System
Resources | Services | Documentation |
|
Home | Products
and Services | End
Markets | Support | Education | Online
Store | Contact
|

(C) Copyright 1994-2004 Xilinx, Inc. All Rights
Reserved