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IEEE
Std 1149.1
IEEE
Std 1532
Device
& Software Support
Automatic
Test Equipment

SVF
JEDEC
BSDL

IEEE Std 1149.1 Background

The Boundary Scan/JTAG, formally known as IEEE/ANSI standard 1149.1_1190
is a set of design rules, which facilitate the testing, device
programming and debug at the chip, board and systems level. The
standard came about as a result of the efforts of a Joint Test
Action Group (JTAG) formed by several North American and European
companies. IEEE Std 1149.1 was originally developed as an on-chip
test infrastructure capable of extending the lifetime of available
automatic test equipment (ATE). A wealth of information on the
standard is available from the Texas Instruments
Boundary Scan Page. This methodology of incorporating
design-for-test allows complete control and access to the boundary
pins of a device without the need for a bed-of -nails or other test
equipment. Each JTAG compliant device includes on the input/output
pins a boundary cell (Figure 1) that under normal conditions is
transparent and inactive allowing signals to pass normally. When the
device is placed in the test mode, input signals can be captured for
later analysis and output signals can be set to affect other devices
on the board.

Access is required to only 4 (or 5) pins on a device, regardless
of the packaging constraints. These pins define a Test
Access Port (TAP) that enables operation of the on-chip test
infrastructure that is used to ensure that:

All components on a printed circuit board are mounted properly
and in the right place.

All interconnections between components are as described in
the design.

So simply stated, the IEEE Std 1449.1 defines a serial protocol
that requires 4 (and optionally 5) pins on each compliant device.
These pins are as follows:

TCK - This is a clock signal that synchronizes the 1149.1
internal state machine operations.

TMS - This is the 1149.1 internal state machine mode select
signal. This signal is sampled at the rising edge of TCK to
determine the next state machine state.

TDI - This is the 1149.1 data input pin. When the internal
state machine is in the correct state, this signal is sampled at
the rising edge of TCK and shifted into the device's test or
programming logic.

TDO - This is the 1149.1 data output pin. When the internal
state machine is in the correct state, this signal represents the
data shifted out of the device's test or programming logic. The
output data is valid on the falling edge of TCK.

TRST (optional) - This is the 1149.1 asynchronous reset pin.
When driven low, the internal state machine advances immediately
to the reset state. Since the pin is optional and pins are
generally high cost additions to devices, it is infrequently used.
In addition, the internal state machine (as defined by the
standard) has a well defined synchronous reset mechanism.

The pins of the TAP drive a 16-state controller (state machine).
The state machine transitions between states according to the value
of the TMS signal value on the rising edge of TCK. The state machine
is illustrated in the diagram below.

The `0' and `1' along the transition arcs represents the state of
the TMS signal at the rising edge of TCK.

The 1149.1 standard defines that TDI is valid and shifted in (and
TDO valid and shifted out) only in the Shift-DR or Shift-IR states.
The Shift-IR state selects the device instruction register between
TDI and TDO. Depending on the instruction selected different data
registers are activated. When in Shift-DR, the data register
appropriate for the previously entered instruction is selected
between TDI and TDO. The default data register is the mandatory
1-bit bypass register.

An external file known as the BSDL (Boundary-Scan Description
Language) file defines the properties and characteristics of any
single device's boundary-scan logic. These files are supplied by the
IC manufacturer and are used in the generation of any algorithmic
description of the operation of the IEEE 1149.1 compliant device.

Multiple boundary-scan devices are linked up serially in a daisy
chain. Each device shares the same TCK and TMS. The TDO of one
device links to the TDI of the next. Since all devices share the
same TCK and TMS, all devices sequence through the TAP controller
synchronously and concurrently. All devices are therefore in the
same TAP controller state at the same time. When shifting data (in
the Shift-IR or Shift-DR state) into the boundary-scan chain, all
devices have registers internally linked between their TDI and TDO
pins. This results in what appears to be a single shift register of
a fixed length from the system TDI pin to the system TDO.

IEEE Std 1532 Configuration and Programming
Standard

Newly designed systems utilizing state-of-the-art PLDs and
Configuration PROMs demand the best programming and configuration
techniques. IEEE Std 1532 specification enables designers to
concurrently program multiple devices, minimize programming times
with enhanced silicon features, and produce robust systems that are
more easily maintained. This new standard paves the way for easy
hardware upgrades by providing a robust and reliable programming
environment.

The IEEE Std 1532 specification was developed to make configuring
any conforming PLD simpler and easier even in a remote environment.
Its unified approach to programming virtually eliminates any device
programming uncertainties and guarantees orderly system startup,
even after power failure. It allows users to easily implement field
diagnostics and new features to extend product life cycles and lower
field maintenance costs.

Programming and algorithm data are kept separate, either one can
be changed without effecting the other eliminating the need to
recompile every time a change is made to a design. Separating the
algorithm from data also allows boundary scan tools and automatic
test equipment to maximize programming efficiency and minimize
programming times lowering production costs.

IEEE Std 1532 features well defined system level instructions
that make enhancements like concurrent programming simple to
implement further reducing programming times. By utilizing these
simplified instructions, designers can reduce time to market and
focus their attention on system features and design optimization
rather than configuration concerns.

Device and Software Support:

The following devices and series of products can take full
advantage of the IEEE 1532 Std specification (see IEEE Std 1532 BSDL
files):

CoolRunner™-II

Spartan™ series FPGAs and Spartan™-II series FPGAs

Virtex™ series FPGAs, Virtex™-II series FPGAs and Virtex™-II
Pro

System ACE™

Xilinx also offers the world's first IEEE Std 1532 programming
engine J
Drive which can be downloaded free.

Automatic Test Equipment (ATE), Third Party
Tool and In Line Programmer Participants:

Major telecommunications and consumer electronics companies were
involved to insure that the standard met their needs across a wide
variety of different programmable devices. Major Automatic Test
Equipment manufacturers (Agilent and Teradyne), Boundary Scan tool
suppliers (ASSET Intertech, Corelis, Intellitech, and JTAG
Technologies) along with in-line programmer suppliers (Data I/O and
BP Microsystems) participated in the development of IEEE-STD-1532.

Serial Vector Format (SVF)

Serial
Vector Format (SVF) Specification - The de facto standard for
interchange of boundary scan based stimulus information. Note that
this is not an open standard. It is currently copyrighted and
controlled by Asset Intertech but freely distributed.

JEDEC

The
JEDEC Programming File - more formally known as JESD3-C
Standard Data Transfer Format Between Data Preparation System and
Programmable Logic Device Programmer.

The
JEDEC Chain Description File - more formally known as
JESD32 Standard for Chain Description File. This file
format is meant describe the connection of arbitrary programmable
devices in a serial chain. It is somewhat confused in execution,
precariously trying to balance a description of both non-1149.1
and 1149.1 types of serial chains in the same language. It also
notably is unable to describe complex boundary scan chain
configurations like hierarchical or multidrop types of
architectures

BSDL

Boundary Scan Description Language (BSDL) Standard 1149.lb is used to
describe the 1149.1 TAP Controller and boundary scan register on a
JTAG 1149.1 boundary scan compliant device. BSDL is also implemented
as a subset of the VHDL standard. Xilinx extensively test and
verifies each BSDL
File.

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