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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| Instr-Concurente.pdf | 2017-03-03 21:20 | 648K | |
| Instr-Secventiale.pdf | 2017-03-03 21:21 | 658K | |
| SSC_pkg.zip | 2017-04-18 14:51 | 1.3K | |
| proc_RISC.zip | 2017-05-11 20:51 | 7.2K | |
| implem_RISC.zip | 2017-05-21 14:29 | 10K | |
| Planse-RISC.pdf | 2018-03-15 11:29 | 618K | |
| Proiectare-Structurala.pdf | 2018-03-15 11:31 | 559K | |
| clock.zip | 2020-07-31 19:49 | 8.1K | |
| Proiectare-FPGA.pdf | 2020-09-23 13:08 | 8.3M | |
| Simulare.pdf | 2020-10-02 19:43 | 6.8M | |
| Automate-Stare.pdf | 2020-10-10 12:44 | 3.8M | |
| Aritm-Combinationala.pdf | 2020-10-17 11:45 | 4.4M | |
| Aritm-Secventiala.pdf | 2020-10-29 22:40 | 5.9M | |
| Testare-Depanare.pdf | 2020-11-13 20:11 | 6.1M | |
| Proiectare-Interfata.pdf | 2020-11-27 15:05 | 5.3M | |
| Procesor-RISC.pdf | 2020-12-11 18:56 | 7.6M | |