dec7seg Project Status
Project File: lab2.xise Parser Errors: No Errors
Module Name: dec7seg Implementation State: Placed and Routed
Target Device: xc3s500e-4fg320
  • Errors:
 No Errors
Product Version:ISE 14.7
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
 All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
 0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 7 9,312 1%  
Number of occupied Slices 4 4,656 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 7 9,312 1%  
Number of bonded IOBs 15 232 6%  
Average Fanout of Non-Clock Nets 3.18      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Oct 18 14:57:57 2023000
Translation ReportCurrentWed Oct 18 14:58:32 2023000
Map ReportCurrentWed Oct 18 14:58:39 2023002 Infos (2 new)
Place and Route ReportCurrentWed Oct 18 14:58:48 2023001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Oct 18 14:58:52 2023006 Infos (6 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 11/05/2025 - 14:20:45