System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 < data not available > < data not available > < data not available >
Path C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt;
C:\Xilinx\14.7\ISE_DS\common\lib\nt;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Program Files (x86)\AOMEI Backupper;
C:\Program Files\dotnet\;
C:\Users\sebas\AppData\Local\Microsoft\WindowsApps		 < data not available > < data not available > < data not available >
XILINX C:\Xilinx\14.7\ISE_DS\ISE\ < data not available > < data not available > < data not available >
XILINX_DSP C:\Xilinx\14.7\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_EDK C:\Xilinx\14.7\ISE_DS\EDK < data not available > < data not available > < data not available >
XILINX_PLANAHEAD C:\Xilinx\14.7\ISE_DS\PlanAhead < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   lab22.prj  
-ifmt   mixed MIXED
-ofn   lab22  
-ofmt   NGC NGC
-p   xc3s500e-4-fg320  
-top   lab22  
-opt_mode Optimization Goal Speed SPEED
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized as_optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets ALLCLOCKNETS
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-mult_style   Auto AUTO
-iobuf   YES YES
-max_fanout   500 500
-bufg   24 24
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Yes YES
-use_sync_set   Yes YES
-use_sync_reset   Yes YES
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i5-7300U CPU @ 2.60GHz/2712 MHz <  data not available  > <  data not available  > <  data not available  >
Host DESKTOP-QQT7U22 <  data not available  > <  data not available  > <  data not available  >
OS Name Microsoft , 64-bit <  data not available  > <  data not available  > <  data not available  >
OS Release major release (build 9200) <  data not available  > <  data not available  > <  data not available  >