lab3vhdl Project Status
Project File:	lab3.xise	Parser Errors:	No Errors
Module Name:	lab3vhdl	Implementation State:	Placed and Routed
Target Device:	xc3s500e-4fg320	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of 4 input LUTs	8	9,312	1%
Number of occupied Slices	5	4,656	1%
Number of Slices containing only related logic	5	5	100%
Number of Slices containing unrelated logic	0	5	0%
Total Number of 4 input LUTs	8	9,312	1%
Number of bonded IOBs	16	232	6%
Average Fanout of Non-Clock Nets	2.00

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Wed Oct 25 18:18:24 2023	0	0	0
Translation Report	Current	Wed Oct 25 18:18:29 2023	0	0	0
Map Report	Current	Wed Oct 25 18:18:33 2023	0	0	2 Infos (0 new)
Place and Route Report	Current	Wed Oct 25 18:18:41 2023	0	0	2 Infos (1 new)
Power Report
Post-PAR Static Timing Report	Current	Wed Oct 25 18:18:44 2023	0	0	6 Infos (0 new)
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 11/12/2025 - 14:21:19