| mux2_1 Project Status | |||
| Project File: | lab4.xise | Parser Errors: | No Errors |
| Module Name: | mux2_1 | Implementation State: | Placed and Routed |
| Target Device: | xc3s500e-4fg320 |
|
No Errors |
| Product Version: | ISE 14.7 |
|
No Warnings |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
|
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of 4 input LUTs | 8 | 9,312 | 1% | ||
| Number of occupied Slices | 4 | 4,656 | 1% | ||
| Number of Slices containing only related logic | 4 | 4 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 4 | 0% | ||
| Total Number of 4 input LUTs | 8 | 9,312 | 1% | ||
| Number of bonded IOBs | 25 | 232 | 10% | ||
| Average Fanout of Non-Clock Nets | 1.41 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Wed Nov 1 17:06:39 2023 | 0 | 0 | 0 | |
| Translation Report | Current | Wed Nov 1 17:06:43 2023 | 0 | 0 | 0 | |
| Map Report | Current | Wed Nov 1 17:06:46 2023 | 0 | 0 | 2 Infos (0 new) | |
| Place and Route Report | Current | Wed Nov 1 17:06:53 2023 | 0 | 0 | 2 Infos (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Wed Nov 1 17:06:56 2023 | 0 | 0 | 6 Infos (0 new) | |
| Bitgen Report | Out of Date | Wed Nov 1 17:04:55 2023 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Current | Wed Oct 29 19:02:16 2025 | |
| WebTalk Log File | Current | Wed Oct 29 19:02:17 2025 | |