Dr. Baruch Zoltan Francisc
Professor




BARUCH, ZOLTAN FRANCISC

STRUCTURE OF COMPUTER SYSTEMS
WITH APPLICATIONS


U. T. PRES, Cluj-Napoca, 2003, ISBN 973-8335-89-2 (302 pages)










TABLE OF CONTENTS


1. DIDACTIC COMPUTER

1.1. OVERVIEW OF THE DIDACTIC COMPUTER
1.2. INSTRUCTIONS OF THE DIDACTIC COMPUTER

1.2.1. Word Structure. 1.2.2. Instruction Set. 1.2.3. Example Programs

1.3. STRUCTURE OF THE DIDACTIC COMPUTER

1.3.1. General Structure. 1.3.2. Control Signals. 1.3.3. Detailed Structure

1.4. APPLICATIONS

2. BINARY MULTIPLICATION AND DIVISION CIRCUITS

2.1. BINARY MULTIPLICATION

2.1.1. Binary Multiplication Methods. 2.1.2. Direct Multiplication. 2.1.3. Booth Multiplication. 2.1.4. Multiplication on Groups of Bits

2.2. BINARY DIVISION

2.2.1. Principle of Binary Division. 2.2.2. Binary Division Methods. 2.2.3. Restoring Division. 2.2.4. Nonrestoring Division

2.3. APPLICATIONS

3. DECIMAL MULTIPLICATION AND DIVISION CIRCUITS

3.1. DECIMAL MULTIPLICATION

3.1.1. Repeated-Addition Method. 3.1.2. Nine-Multiples-of-Multiplicand Method. 3.1.3. Right-and-Left-Hand Components Method

3.2. DECIMAL DIVISION

3.2.1. Restoring Division. 3.2.2. Nonrestoring Division. 3.2.3. Nine-Multiples-of-Divisor Method

3.3. APPLICATIONS

4. MICROPROGRAMMED COMPUTERS

4.1. PRINCIPLE OF MICROPROGRAMMED COMPUTERS

4.1.1. Introduction. 4.1.2. Horizontal and Vertical Microprogramming. 4.1.3. Structure of a Microprogrammed Control Unit

4.2. EXAMPLE OF COMPUTER WITH HORIZONTAL MICROPROGRAMMING

4.2.1. Datapath Structure. 4.2.2. Microinstruction Format. 4.2.3. Microinstruction Sequencing. 4.2.4. The Microassembly Language

4.3. EXAMPLE OF COMPUTER WITH VERTICAL MICROPROGRAMMING

4.3.1. Vertical Microinstructions. 4.3.2. Structure of Control Section

4.4. APPLICATIONS

5. BASIC ELEMENTS OF THE VHDL LANGUAGE

5.1. DESIGN UNITS
5.2. ENTITIES

5.2.1. Entity Names: Identifiers. 5.2.2. Entity Declarations. 5.2.3. Signals and Ports: The Concept of a Signal; Port Declarations; Port Modes; Port Types. 5.2.4. Generics

5.3. ARCHITECTURES

5.3.1. Architecture Declaration. 5.3.2. Signal Declaration. 5.3.3. Signal Assignments. 5.3.4. Styles of Architectural Descriptions: Functional Descriptions; Dataflow Descriptions; Structural Descriptions; Comparing Architectural Descriptions

5.4. MODELING FOR SIMULATION

5.4.1. Event-Driven Simulation. 5.4.2. Signal Drivers. 5.4.3. Simulation Cycle. 5.4.4. Multiple Drivers and Resolution Functions

5.5. MODELING FOR SYNTHESIS
5.6. APPLICATIONS

6. SEQUENTIAL AND CONCURRENT STATEMENTS IN THE VHDL LANGUAGE

6.1. SEQUENTIAL STATEMENTS

6.1.1. Processes: Structure and Execution of a Process; Processes with Incomplete Sensitivity Lists; Wait Statement; Combinational and Sequential Processes. 6.1.2. Sequential Signal Assignment Statement: Sequential Assignment Statement Execution; Feedback; Inertial Delay; Transport Delay. 6.1.3. Variables: Declaring and Initializing Variables; Variable Assignment Statement. 6.1.4. If Statement: Syntax and Execution of an if Statement; Synthesis Interpretation of an if Statement; Incomplete if Statements; If Statements with Variables. 6.1.5. Case Statement. 6.1.6. Loop Statements: Loop Statement; While loop Statement; For loop Statement; Next Statement; Exit Statement. 6.1.7. Sequential assert Statement

6.2. CONCURRENT STATEMENTS

6.2.1. Structure and Execution of an Architecture. 6.2.2. Processes. 6.2.3. Concurrent Signal Assignment Statements: Simple Signal Assignment; Conditional Signal Assignment; Selected Signal Assignment; Block Statement; Concurrent assert Statement

6.3. EXAMPLES OF COMBINATIONAL CIRCUITS

6.3.1. Multiplexers. 6.3.2. Priority Encoders

6.4. EXAMPLES OF SEQUENTIAL CIRCUITS

6.4.1. Synchronous and Asynchronous Sequential Circuits. 6.4.2. Flip-Flops. 6.4.3. Registers. 6.4.4. Counters. 6.4.5. Resetting Synchronous Logic. 6.4.6. Three-State Buffers and Bidirectional Signals

6.5. APPLICATIONS

7. STATE MACHINES IN THE VHDL LANGUAGE

7.1. DESIGN EXAMPLE

7.1.1. Traditional Design. 7.1.2. Design Using the VHDL Language

7.2. DESIGN OF A MEMORY CONTROLLER
7.3. TECHNIQUES TO GENERATE THE OUTPUT SIGNALS

7.3.1. Outputs Decoded from State Bits. 7.3.2. Outputs Decoded in Parallel Output Registers. 7.3.3. Outputs Encoded within State Bits. 7.3.4. One-Hot Encoding

7.4. MEALY STATE MACHINES
7.5. OTHER DESIGN CONSIDERATIONS

7.5.1. State Encoding Using Enumeration Types. 7.5.2. Explicit State Encoding. 7.5.3. Fault Tolerance for One-Hot Machines

7.6. APPLICATIONS

8. STRUCTURAL DESIGN IN THE VHDL LANGUAGE

8.1. ADVANTAGES OF STRUCTURAL DESIGN
8.2. ELEMENTS OF A STRUCTURAL DESCRIPTION

8.2.1. Example of Structural Description. 8.2.2. Component Declaration. 8.2.3. Component Instantiation. 8.2.4. Direct Entity Instantiation. 8.2.5. Configuration Specification

8.3. LIBRARIES
8.4. PACKAGES

8.4.1. Package Declaration. 8.4.2. Package Body. 8.4.3. Packages with Component Declarations

8.5. GENERICS AND PARAMETERIZED COMPONENTS

8.5.1. Principle of Generics. 8.5.2. Defining Generic Entities. 8.5.3. Using Generic Components. 8.5.4. Types of Generic Parameters. 8.5.5. Building a Library of Components

8.6. GENERATE STATEMENT

8.6.1. For generate Statement. 8.6.2. If generate Statement. 8.6.3. Component Instances in Generate Statements

8.7. APPLICATIONS

9. SUBPROGRAMS IN THE VHDL LANGUAGE

9.1. THE ROLE OF SUBPROGRAMS
9.2. FUNCTIONS

9.2.1. Function Definition. 9.2.2. Using Functions. 9.2.3. Initial Values. 9.2.4. Functions with Unconstrained Parameters. 9.2.5. Unconstrained Return Values. 9.2.6. Multiple Return Statements. 9.2.7. Function Overloading. 9.2.8. Type Conversion Functions: Built-In Type Conversions; User-Defined Type Conversions. 9.2.9. Functions as Alternative to Component Instantiation. 9.2.10. Problematic Functions for Synthesis. 9.2.11. Defining Operators as Functions: Built-In Operators; Operator Overloading. 9.2.12. Standard Functions. 9.2.13. Placement of Function Definitions

9.3. PROCEDURES

9.3.1. Procedure Definition. 9.3.2. Procedure Call. 9.3.3. Procedures with Unconstrained Parameters. 9.3.4. Parameters of Mode Inout. 9.3.5. Signals Used as Parameters. 9.3.6. Procedure Overloading

9.4. APPLICATIONS

10. THE DLX COMPUTER

10.1. ARCHITECTURE OF THE DLX COMPUTER

10.1.1. Register Set. 10.1.2. Structure of the Pipelined Datapath and Instruction Execution. 10.1.3. Hazards

10.2. THE DLX ASSEMBLY LANGUAGE

10.2.1. Expressions. 10.2.2. Directives. 10.2.3. Instruction Set: Data Transfer Instructions; Arithmetic and Logical Instructions; Control Instructions; Floating-Point Instructions

10.3. THE WinDLX SIMULATOR

10.3.1. Overview. 10.3.2. System Function Calls: Open a File; Close a File; Read a Block from a File; Write a Block to a File; Formatted Output to the Standard Output Device

10.4. USING THE WinDLX SIMULATOR

10.4.1. Starting and Configuring the Simulator. 10.4.2. Loading the Test Programs. 10.4.3. Simulating: Pipeline Window; Code Window; Clock Cycle Diagram Window; Breakpoint Window; Register Window; Statistics Window

10.5. APPLICATIONS

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